alt_sld_fab

2017.03.21.13:19:45 Datasheet
Overview
Memory Map

alt_sld_fab

alt_sld_fab v16.1


Parameters

DESIGN_HASH 151dea5954e7389f745b
NODE_COUNT 5
MAX_WIDTH 33
SETTINGS {fabric sld dir agent mfr_code 110 type_code 128 version 1 instance -1 ir_width 1 bridge_agent 0 prefer_host { } psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 psig 9b67919e} {fabric sld dir agent mfr_code 110 type_code 0 version 6 instance 4 ir_width 10 psig 9b67919e}
CLOCKS {id {} } {id {} } {id {} } {id {} } {id {} }
AGENTS
EP_INFOS {hpath {soc_system:u0|soc_system_jtag_uart:jtag_uart|alt_jtag_atlantic:soc_system_jtag_uart_alt_jtag_atlantic|altera_sld_agent_endpoint:inst|altera_fabric_endpoint:ep} } {hpath {soc_system:u0|soc_system_fpga_only_master:fpga_only_master|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst} } {hpath {soc_system:u0|soc_system_fpga_only_master:hps_only_master|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_sld_node:node|sld_virtual_jtag_basic:sld_virtual_jtag_component|sld_virtual_jtag_impl:sld_virtual_jtag_impl_inst} } {hpath {sld_signaltap:auto_signaltap_0} } {hpath {sld_signaltap:auto_signaltap_4} }
MIRROR 0
TOP_HUB 1
COMPOSED_SETTINGS {fabric sld dir agent mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host {} } {fabric sld dir agent mfr_code 110 type_code 0 version 6 instance 4 ir_width 10 bridge_agent 0 prefer_host {} }
DEVICE_FAMILY CYCLONEV
AUTO_DEVICE Unknown
AUTO_DEVICE_SPEEDGRADE Unknown
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_presplit

altera_super_splitter v16.1


Parameters

MAX_WIDTH 33
SEND_WIDTHS 3 5 5 12 12
RECEIVE_WIDTHS 24 26 26 33 33
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_splitter

altera_sld_splitter v16.1
alt_sld_fab_presplit pass   alt_sld_fab_splitter
  nodes
alt_sld_fab_sldfabric clock_0  
  clock_0
node_0  
  node_0
clock_1  
  clock_1
node_1  
  node_1
clock_2  
  clock_2
node_2  
  node_2
clock_3  
  clock_3
node_3  
  node_3
clock_4  
  clock_4
node_4  
  node_4


Parameters

FRAGMENTS {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 1 23} {irq irq out 1 1} {ir_out ir_out out 1 2} } clock clock assign {debug.controlledBy {link_0} } moduleassign {debug.virtualInterface.link_0 {debug.endpointLink {fabric sld index 1} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 3 23} {irq irq out 1 1} {ir_out ir_out out 3 2} } clock clock assign {debug.controlledBy {link_1} } moduleassign {debug.virtualInterface.link_1 {debug.endpointLink {fabric sld index 2} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 3 23} {irq irq out 1 1} {ir_out ir_out out 3 2} } clock clock assign {debug.controlledBy {link_2} } moduleassign {debug.virtualInterface.link_2 {debug.endpointLink {fabric sld index 3} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 10 23} {irq irq out 1 1} {ir_out ir_out out 10 2} } clock clock assign {debug.controlledBy {link_3} } moduleassign {debug.virtualInterface.link_3 {debug.endpointLink {fabric sld index 4} } } } } {{name clock type clock dir end ports { {tck clk in 1 0} } } {name node type conduit dir end ports { {tms tms in 1 1} {tdi tdi in 1 2} {tdo tdo out 1 0} {ena ena in 1 3} {usr1 usr1 in 1 4} {clr clr in 1 5} {clrn clrn in 1 6} {jtag_state_tlr jtag_state_tlr in 1 7} {jtag_state_rti jtag_state_rti in 1 8} {jtag_state_sdrs jtag_state_sdrs in 1 9} {jtag_state_cdr jtag_state_cdr in 1 10} {jtag_state_sdr jtag_state_sdr in 1 11} {jtag_state_e1dr jtag_state_e1dr in 1 12} {jtag_state_pdr jtag_state_pdr in 1 13} {jtag_state_e2dr jtag_state_e2dr in 1 14} {jtag_state_udr jtag_state_udr in 1 15} {jtag_state_sirs jtag_state_sirs in 1 16} {jtag_state_cir jtag_state_cir in 1 17} {jtag_state_sir jtag_state_sir in 1 18} {jtag_state_e1ir jtag_state_e1ir in 1 19} {jtag_state_pir jtag_state_pir in 1 20} {jtag_state_e2ir jtag_state_e2ir in 1 21} {jtag_state_uir jtag_state_uir in 1 22} {ir_in ir_in in 10 23} {irq irq out 1 1} {ir_out ir_out out 10 2} } clock clock assign {debug.controlledBy {link_4} } moduleassign {debug.virtualInterface.link_4 {debug.endpointLink {fabric sld index 5} } } } }
EXAMPLE
ADD_INTERFACE_ASGN 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_jtagpins

altera_jtag_pins_bridge v16.1


Parameters

deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_sldfabric

altera_sld_jtag_hub v16.1
alt_sld_fab_jtagpins clock   alt_sld_fab_sldfabric
  clock
node  
  node
clock_0   alt_sld_fab_splitter
  clock_0
node_0  
  node_0
clock_1  
  clock_1
node_1  
  node_1
clock_2  
  clock_2
node_2  
  node_2
clock_3  
  clock_3
node_3  
  node_3
clock_4  
  clock_4
node_4  
  node_4
ident   alt_sld_fab_ident
  ident_0


Parameters

DEVICE_FAMILY CYCLONEV
SETTINGS {mfr_code 110 type_code 128 version 1 instance 0 ir_width 1 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 132 version 1 instance 0 ir_width 3 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 132 version 1 instance 1 ir_width 3 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 0 version 6 instance 0 ir_width 10 bridge_agent 0 prefer_host {} } {mfr_code 110 type_code 0 version 6 instance 4 ir_width 10 bridge_agent 0 prefer_host {} }
COUNT 5
N_SEL_BITS 3
N_NODE_IR_BITS 10
NODE_INFO 0011000000000000011011100000010000110000000000000110111000000000000011000010000001101110000000010000110000100000011011100000000000001100000000000110111000000000
COMPILATION_MODE 0
BROADCAST_FEATURE 1
FORCE_IR_CAPTURE_FEATURE 1
FORCE_PRE_1_4_FEATURE 0
NEGEDGE_TDO_LATCH 1
ENABLE_SOFT_CORE_CONTROLLER 0
TOP_HUB 1
CONN_INDEX 0
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)

alt_sld_fab_ident

altera_connection_identification_hub v16.1
alt_sld_fab_sldfabric ident   alt_sld_fab_ident
  ident_0


Parameters

DESIGN_HASH 151dea5954e7389f745b
COUNT 1
SETTINGS {width 4 latency 0}
deviceFamily UNKNOWN
generateLegacySim false
  

Software Assignments

(none)
generation took 0,03 seconds rendering took 0,06 seconds