
State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:sysid_qsys_control_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_fpga_only_master:fpga_only_master|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state
Name state.READ_SEND_WAIT state.READ_SEND_ISSUE state.READ_DATA_WAIT state.READ_CMD_WAIT state.READ_ASSERT state.RETURN_PACKET state.WRITE_WAIT state.GET_WRITE_DATA state.GET_ADDR4 state.GET_ADDR3 state.GET_ADDR2 state.GET_ADDR1 state.GET_SIZE2 state.GET_SIZE1 state.GET_EXTRA state.0000 
state.0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
state.GET_EXTRA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
state.GET_SIZE1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
state.GET_SIZE2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
state.GET_ADDR1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
state.GET_ADDR2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
state.GET_ADDR3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
state.GET_ADDR4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
state.GET_WRITE_DATA 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
state.WRITE_WAIT 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
state.RETURN_PACKET 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
state.READ_ASSERT 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
state.READ_CMD_WAIT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
state.READ_DATA_WAIT 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
state.READ_SEND_ISSUE 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
state.READ_SEND_WAIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_fpga_only_master:hps_only_master|altera_avalon_packets_to_master:transacto|packets_to_master:p2m|state
Name state.READ_SEND_WAIT state.READ_SEND_ISSUE state.READ_DATA_WAIT state.READ_CMD_WAIT state.READ_ASSERT state.RETURN_PACKET state.WRITE_WAIT state.GET_WRITE_DATA state.GET_ADDR4 state.GET_ADDR3 state.GET_ADDR2 state.GET_ADDR1 state.GET_SIZE2 state.GET_SIZE1 state.GET_EXTRA state.0000 
state.0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
state.GET_EXTRA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
state.GET_SIZE1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
state.GET_SIZE2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
state.GET_ADDR1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
state.GET_ADDR2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
state.GET_ADDR3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
state.GET_ADDR4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
state.GET_WRITE_DATA 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
state.WRITE_WAIT 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
state.RETURN_PACKET 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
state.READ_ASSERT 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
state.READ_CMD_WAIT 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
state.READ_DATA_WAIT 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
state.READ_SEND_ISSUE 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 
state.READ_SEND_WAIT 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:led_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:dipsw_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_fpga_only_master:fpga_only_master|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state
Name read_state.ST_HEADER read_state.ST_READ_DATA read_state.ST_PADDED 
read_state.ST_HEADER 0 0 0 
read_state.ST_PADDED 1 0 1 
read_state.ST_READ_DATA 1 1 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_fpga_only_master:fpga_only_master|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state
Name write_state.ST_WRITE_DATA write_state.ST_HEADER_2 write_state.ST_HEADER_1 write_state.ST_BYPASS 
write_state.ST_BYPASS 0 0 0 0 
write_state.ST_HEADER_1 0 0 1 1 
write_state.ST_HEADER_2 0 1 0 1 
write_state.ST_WRITE_DATA 1 0 0 1 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_fpga_only_master:hps_only_master|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|read_state
Name read_state.ST_HEADER read_state.ST_READ_DATA read_state.ST_PADDED 
read_state.ST_HEADER 0 0 0 
read_state.ST_PADDED 1 0 1 
read_state.ST_READ_DATA 1 1 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_fpga_only_master:hps_only_master|altera_avalon_st_jtag_interface:jtag_phy_embedded_in_jtag_master|altera_jtag_dc_streaming:normal.jtag_dc_streaming|altera_jtag_streaming:jtag_streaming|write_state
Name write_state.ST_WRITE_DATA write_state.ST_HEADER_2 write_state.ST_HEADER_1 write_state.ST_BYPASS 
write_state.ST_BYPASS 0 0 0 0 
write_state.ST_HEADER_1 0 0 1 1 
write_state.ST_HEADER_2 0 1 0 1 
write_state.ST_WRITE_DATA 1 0 0 1 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:jtag_uart_avalon_jtag_slave_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:button_pio_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_1_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 

State Machine - |HPS_CONTROL_FPGA_LED|soc_system:u0|soc_system_mm_interconnect_0:mm_interconnect_0|altera_merlin_burst_adapter:onchip_memory2_0_s1_burst_adapter|altera_merlin_burst_adapter_13_1:altera_merlin_burst_adapter_13_1.burst_adapter|state
Name state.ST_IDLE state.ST_UNCOMP_WR_SUBBURST state.ST_UNCOMP_TRANS state.ST_COMP_TRANS 
state.ST_IDLE 0 0 0 0 
state.ST_COMP_TRANS 1 0 0 1 
state.ST_UNCOMP_TRANS 1 0 1 0 
state.ST_UNCOMP_WR_SUBBURST 1 1 0 0 
