Command module verilog

Модуль предназначен для разбора приходящих команд. В зависимости от команды, значение записывается в определенный регистр. Также заданные многие константы.

В последней строке генерится сигнал прихода новой команды.

module command(
input clk9600,
input [7:0]adress_from_UART,
input [15:0]UART_to_SPI,

output reg [7:0]adress,
output reg [1:0]adress2,
output reg [1:0]adressN,
output reg [15:0]D4_start = 38 ,
output reg [15:0]D4_stop = 2 ,
output reg [15:0]D7_start = 323,
output reg [15:0]D7_stop  = 580,

output reg [15:0]D10_start = 19,
output reg [15:0]D10_stop ,
output reg UART_to_SPI_Update,
output reg reverse = 0,
output reg [7:0]number_ADC = 0
);

reg [13:0]UART_to_SPI_last;


always @ (posedge clk9600) begin

	case(adress_from_UART)
		97: 	begin adress <= 8'b00110001;	adressN <= 0; end
		98:	begin adress <= 8'b00110010;	adressN <= 0; end
		99: 	begin adress <= 8'b00110001;	adressN <= 1; end
		100:	begin adress <= 8'b00110010;	adressN <= 1; end
		101: 	begin adress <= 8'b00110100;	adressN <= 1; end
		102: 	begin adress <= 8'b00111000;	adressN <= 1; end
		103:	begin adress <= 8'b00110001;	adressN <= 2; end
		104:	begin adress <= 8'b00110010;	adressN <= 2; end
		105:	begin adress <= 8'b00110100;	adressN <= 2; end
		106:	begin adress <= 8'b00111000;	adressN <= 2; end
		107:	 D4_start 	<= UART_to_SPI;
		108:	 D4_stop 	<= UART_to_SPI;
		109:	 D7_start 	<= UART_to_SPI;
		110:	 D7_stop 	<= UART_to_SPI;
		111:	 D10_start 	<= UART_to_SPI;
		112:	 D10_stop 	<= UART_to_SPI;
		120:	begin 
					adress <= 8'b10000000;
					if (UART_to_SPI == 1)
					adress2 <= 1;
					else 
					adress2 <= 0;
				end
		121: begin 
					if (UART_to_SPI == 1)
					adressN <= 1;
					else 
					adressN <= 0;
				end
		65: reverse <= UART_to_SPI[0];
		66: number_ADC <= UART_to_SPI[7:0];	
	endcase	
	
	UART_to_SPI_last <= UART_to_SPI;
	
	if (UART_to_SPI_last != UART_to_SPI && adress_from_UART>96 && adress_from_UART < 107)
		UART_to_SPI_Update <= 1;
	else 
		UART_to_SPI_Update <= 0;
		
end


endmodule

module command(

input clk9600,

input [7:0]adress_from_UART,

input [15:0]UART_to_SPI,

output reg [7:0]adress,

output reg [1:0]adress2,

output reg [1:0]adressN,

output reg [15:0]D4_start = 38 ,

output reg [15:0]D4_stop = 2 ,

output reg [15:0]D7_start = 323,

output reg [15:0]D7_stop = 580,

output reg [15:0]D10_start = 19,

output reg [15:0]D10_stop ,

output reg UART_to_SPI_Update,

output reg reverse = 0,

output reg [7:0]number_ADC = 0

);

reg [13:0]UART_to_SPI_last;

always @ (posedge clk9600) begin

case(adress_from_UART)

97: begin adress <= 8'b00110001; adressN <= 0; end

98: begin adress <= 8'b00110010; adressN <= 0; end

99: begin adress <= 8'b00110001; adressN <= 1; end

100: begin adress <= 8'b00110010; adressN <= 1; end

101: begin adress <= 8'b00110100; adressN <= 1; end

102: begin adress <= 8'b00111000; adressN <= 1; end

103: begin adress <= 8'b00110001; adressN <= 2; end

104: begin adress <= 8'b00110010; adressN <= 2; end

105: begin adress <= 8'b00110100; adressN <= 2; end

106: begin adress <= 8'b00111000; adressN <= 2; end

107: D4_start <= UART_to_SPI;

108: D4_stop <= UART_to_SPI;

109: D7_start <= UART_to_SPI;

110: D7_stop <= UART_to_SPI;

111: D10_start <= UART_to_SPI;

112: D10_stop <= UART_to_SPI;

120: begin

adress <= 8'b10000000;

if (UART_to_SPI == 1)

adress2 <= 1;

else

adress2 <= 0;

end

121: begin

if (UART_to_SPI == 1)

adressN <= 1;

else

adressN <= 0;

end

65: reverse <= UART_to_SPI[0];

66: number_ADC <= UART_to_SPI[7:0];

endcase

UART_to_SPI_last <= UART_to_SPI;

if (UART_to_SPI_last != UART_to_SPI && adress_from_UART>96 && adress_from_UART < 107)

UART_to_SPI_Update <= 1;

else

UART_to_SPI_Update <= 0;

end

endmodule

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