TOP module SYSTEM VERILOG

SYSTEM VERILOG Сode top module

Интересная часть кода verillog под Quartus II

Сверху пропущены порты взаимодействия с внешним миром.
Строки 1-26 порты взаимодействия с памятью DRAM размещенной на кристале и созданой Qsys. Через неё ПЛИС переправляет данные на Linux.

В том модуле задействованы следующие подмодули:
pll_0002 pll_inst — синтезирует из 50 MHz 20 MHz;
command — разбирает полученную команду с регистра COM-porta, в значение служебных регистров.
generete_row_and_col_for_cheap — Генерирует сигналы управления для чипа
SPI — передает полученную команду на ЦАПы по SPI

55-61 Синтез частоты для АЦП и опроса пикселей.
64-70 Синтез частоты для SPI
72-98 Здесь 8-битная шина АЦП преобразуется в 64 битные слова памяти.
113-121 выбор АЦП и разрядов АЦП
101-105 — первые два байта в строке, которая записывается в память, Это номер строки.
107-108 — конец строки в пакете помечается 255. Здесь прописано принудительное условие, что это 316 пиксель.
110-111 принудительное замена значения АЦП 255 на 254 для освобождения 255 для конца строки.

Строка 27 служит для вывода регистров на LED. Выбор регистра осуществляется кнопками.

//FPGA Partion
		.led_pio_external_connection_export    ( LED_from_hps	),    //led_pio_external_connection.export
		.dipsw_pio_external_connection_export  ( {30'b1, numCol[0] && numCol[1] && numCol[2] }	),  //dipsw_pio_external_connection.export
		.button_pio_external_connection_export ( KEY	), 											//button_pio_external_connection.export
		.hps_0_h2f_reset_reset_n               (hps_fpga_reset_n )  ,              					//hps_0_h2f_reset.reset_n
		.onchip_memory2_0_clk2_clk             (CLK_20MHZ),             							//onchip_memory2_0_clk2.clk
		.onchip_memory2_0_reset2_reset         (0),         										//onchip_memory2_0_reset2.reset
		.onchip_memory2_0_reset2_reset_req     (0),     											//.reset_req
		.onchip_memory2_0_s2_address           (mem_adress),           								//onchip_memory2_0_s2.address
		.onchip_memory2_0_s2_chipselect        (1),        											//.chipselect
		.onchip_memory2_0_s2_clken             (adc_to_bridge[2] && adc_to_bridge[1] &&  adc_to_bridge[0]), //.clken
		.onchip_memory2_0_s2_write             (numCol[0]),             							//.write
		.onchip_memory2_0_s2_readdata          (connected-to-onchip_memory2_0_s2_readdata),          //.readdata
		.onchip_memory2_0_s2_writedata         (datacount2[63:0]),         							//.writedata
		.onchip_memory2_0_s2_byteenable        (8'b11111111),        								//.byteenable
		.onchip_memory2_1_reset2_reset         (0),         										//onchip_memory2_1_reset2.reset
		.onchip_memory2_1_reset2_reset_req     (0),     											//.reset_req
		.onchip_memory2_1_clk2_clk             (CLK_20MHZ),             							//onchip_memory2_1_clk2.clk
		.onchip_memory2_1_s2_address           (mem_adress),           								//onchip_memory2_1_s2.address
		.onchip_memory2_1_s2_chipselect        (1),        											//.chipselect
		.onchip_memory2_1_s2_clken             (adc_to_bridge[2] && adc_to_bridge[1] &&  adc_to_bridge[0]),//.clken
		.onchip_memory2_1_s2_write             (~numCol[0] ),             							//.write
		.onchip_memory2_1_s2_readdata          (connected-to-onchip_memory2_1_s2_readdata),          //.readdata
		.onchip_memory2_1_s2_writedata         (datacount2[63:0]),         							//.writedata
		.onchip_memory2_1_s2_byteenable        (8'b11111111)         								//.byteenable
 );
assign LED[7:0] =SW[0] ? ( ~KEY[0] ? (~KEY[1] ? LED_from_hps[23:16] : LED_from_hps[15:8] ) : LED_from_hps [7:0]) 
								:( ~KEY[0] ? (~KEY[1] ? D7_start[7:0] : D7_start[15:8] ) : (~KEY[1] ? D7_stop[7:0] : D7_stop[15:8] )) ;
assign mem_adress[12:0] =   numRow[10:2] - 2;


wire 			CLK_20MHZpll;
wire 	[10:0]	numRow;
wire 	[11:0]	numCol;
wire 	[12:0]	mem_adress;
wire 	[15:0]	D10_stop;
wire 	[7:0] 	data_UART;
wire 	[13:0]	UART_to_SPI;
wire 	[7:0] 	adress ;
wire 	[12:0]	adress_from_UART;
wire 	[15:0] 	D10_start;
reg 	[63:0]	datacount;
reg 	[15:0]	count1Mhz;
reg 			clk1Mhz;
reg 	[7:0] 	ADC_E;
reg 	[2:0] 	adc_to_bridge;	
reg 	[63:0]	datacount2; 
reg 	[15:0]	CLK_20MHZpll_count;	
reg 	[10:0]	numRow2;
reg 			CLK_20MHZ;




always @(posedge CLK_20MHZpll)
	if ( CLK_20MHZpll_count == D10_stop) begin
			CLK_20MHZ <= ~CLK_20MHZ;
			CLK_20MHZpll_count <= 0;
			end
			else
			CLK_20MHZpll_count <= CLK_20MHZpll_count + 1;	

always @ (posedge FPGA_CLK3_50) begin
	if (count1Mhz == 2604) begin 
		count1Mhz <= 0;
		clk1Mhz <= ~ clk1Mhz;
	end
		else 
			count1Mhz <= 1 + count1Mhz;
	end

always @ (posedge CLK_20MHZ) begin 
	numRow2 <= numRow;
	
		case(adc_to_bridge)
			0: datacount[7:0] 	<= ADC_E[7:0];
			1: datacount[15:8] 	<= ADC_E[7:0];
			2: datacount[23:16] 	<= ADC_E[7:0];
			3: datacount[31:24] 	<= ADC_E[7:0];
		 	4: datacount[39:32] 	<= ADC_E[7:0];
			5: datacount[47:40] 	<= ADC_E[7:0];
			6: datacount[55:48] 	<= ADC_E[7:0];
			7: datacount[63:56] 	<= ADC_E[7:0]; 
		endcase
		
	
		if (numRow2 == 0 )
			adc_to_bridge <= 0;
		else 
			adc_to_bridge <= adc_to_bridge + 1;
		 
end


always @ (negedge CLK_20MHZ) begin
 	if ( adc_to_bridge == 0) 
		datacount2 <= datacount;
end

always @ (negedge CLK_20MHZ)	
if (numRow == 1 )
		ADC_E <= { 6'b000000, numCol[11:10]};
		else
	if (numRow == 2 )
		ADC_E <= numCol[9:2];
		else 
			if (numRow == 316 )
				ADC_E <= 255;
				else 
					if (ADC ==  255)
						ADC_E <= 254;
					else 
					 case (number_ADC)
					 0:ADC_E <= ADC[7:0];
					 1:ADC_E <= ADC_A[7:0];
					 2:ADC_E <= ADC_A[8:1];
					 3:ADC_E <= ADC_A[9:2];
					 4:ADC_E <= ADC_B[7:0];
					 5:ADC_E <= ADC_B[8:1];
					 6:ADC_E <= ADC_B[9:2];
					 endcase
 
pll_0002 pll_inst (
		.refclk   (FPGA_CLK3_50),   //  refclk.clk
		.rst      (0),      //   reset.reset
		.outclk_0 (CLK_20MHZpll), // outclk0.clk
		.locked   ()          // (terminated)S
	);
	
command(
	.clk9600(clk1Mhz),
	.adress_from_UART(LED_from_hps[23:16]),
	.UART_to_SPI(LED_from_hps[15:0]),
	.adress(adress),
	.adress2(adress2),
	.adressN(adressN),
	.D4_start (D4_start ),
	.D4_stop (D4_stop ),
	.D7_start (D7_start ),
	.D7_stop (D7_stop ),
	.D10_start(D10_start),
	.D10_stop (D10_stop ),
	.UART_to_SPI_Update(UART_to_SPI_Update),
	.reverse(reverse),
	.number_ADC(number_ADC)
		); 




generete_row_and_col_for_cheap (
	.CLK_50MHZ(FPGA_CLK3_50),
	.CLK_20MHZ(CLK_20MHZ),
	.adress_from_UART(LED_from_hps[23:16]),
	.UART_to_SPI(LED_from_hps[15:0]),
	.D1(D1), 		
	.D2(D2), 	//resV
	.D3(D3),
	.D4(D4), 
	.D5(D5),	//clkV
	.D6(D6),	//rstH
	.D7(D7),
	.D8(D8),		//ClkH
	.D9(D9),
	.D10(D10),
	.numRow(numRow),
	.numCol(numCol),
	.D4_start(D4_start),
	.D4_stop(D4_stop),
	.countRow (D7_start ),
	.countCol (D7_stop ),
	.COM_TX_ON(0),
	.clk960(clk960),
	.D10_start(D10_start),
	
	);
	
SPI (
	.data(LED_from_hps[15:0]),
	.adress(adress),
	.adress2(adress2[1:0]),
	.adressN(adressN),
	.data_ready(UART_to_SPI_Update),
	.clk(clk1Mhz),
	.SPI_clk(SPIclk),
	.SPI_data(SPIdata),
	.SPI_en(SPIen)
	);
endmodule

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//FPGA Partion

.led_pio_external_connection_export ( LED_from_hps ), //led_pio_external_connection.export

.dipsw_pio_external_connection_export ( {30'b1, numCol[0] && numCol[1] && numCol[2] } ), //dipsw_pio_external_connection.export

.button_pio_external_connection_export ( KEY ), //button_pio_external_connection.export

.hps_0_h2f_reset_reset_n (hps_fpga_reset_n ) , //hps_0_h2f_reset.reset_n

.onchip_memory2_0_clk2_clk (CLK_20MHZ), //onchip_memory2_0_clk2.clk

.onchip_memory2_0_reset2_reset (0), //onchip_memory2_0_reset2.reset

.onchip_memory2_0_reset2_reset_req (0), //.reset_req

.onchip_memory2_0_s2_address (mem_adress), //onchip_memory2_0_s2.address

.onchip_memory2_0_s2_chipselect (1), //.chipselect

.onchip_memory2_0_s2_clken (adc_to_bridge[2] && adc_to_bridge[1] && adc_to_bridge[0]), //.clken

.onchip_memory2_0_s2_write (numCol[0]), //.write

.onchip_memory2_0_s2_readdata (connected-to-onchip_memory2_0_s2_readdata), //.readdata

.onchip_memory2_0_s2_writedata (datacount2[63:0]), //.writedata

.onchip_memory2_0_s2_byteenable (8'b11111111), //.byteenable

.onchip_memory2_1_reset2_reset (0), //onchip_memory2_1_reset2.reset

.onchip_memory2_1_reset2_reset_req (0), //.reset_req

.onchip_memory2_1_clk2_clk (CLK_20MHZ), //onchip_memory2_1_clk2.clk

.onchip_memory2_1_s2_address (mem_adress), //onchip_memory2_1_s2.address

.onchip_memory2_1_s2_chipselect (1), //.chipselect

.onchip_memory2_1_s2_clken (adc_to_bridge[2] && adc_to_bridge[1] && adc_to_bridge[0]),//.clken

.onchip_memory2_1_s2_write (~numCol[0] ), //.write

.onchip_memory2_1_s2_readdata (connected-to-onchip_memory2_1_s2_readdata), //.readdata

.onchip_memory2_1_s2_writedata (datacount2[63:0]), //.writedata

.onchip_memory2_1_s2_byteenable (8'b11111111) //.byteenable

);

assign LED[7:0] =SW[0] ? ( ~KEY[0] ? (~KEY[1] ? LED_from_hps[23:16] : LED_from_hps[15:8] ) : LED_from_hps [7:0])

:( ~KEY[0] ? (~KEY[1] ? D7_start[7:0] : D7_start[15:8] ) : (~KEY[1] ? D7_stop[7:0] : D7_stop[15:8] )) ;

assign mem_adress[12:0] = numRow[10:2] - 2;

wire CLK_20MHZpll;

wire [10:0] numRow;

wire [11:0] numCol;

wire [12:0] mem_adress;

wire [15:0] D10_stop;

wire [7:0] data_UART;

wire [13:0] UART_to_SPI;

wire [7:0] adress ;

wire [12:0] adress_from_UART;

wire [15:0] D10_start;

reg [63:0] datacount;

reg [15:0] count1Mhz;

reg clk1Mhz;

reg [7:0] ADC_E;

reg [2:0] adc_to_bridge;

reg [63:0] datacount2;

reg [15:0] CLK_20MHZpll_count;

reg [10:0] numRow2;

reg CLK_20MHZ;

always @(posedge CLK_20MHZpll)

if ( CLK_20MHZpll_count == D10_stop) begin

CLK_20MHZ <= ~CLK_20MHZ;

CLK_20MHZpll_count <= 0;

end

else

CLK_20MHZpll_count <= CLK_20MHZpll_count + 1;

always @ (posedge FPGA_CLK3_50) begin

if (count1Mhz == 2604) begin

count1Mhz <= 0;

clk1Mhz <= ~ clk1Mhz;

end

else

count1Mhz <= 1 + count1Mhz;

end

always @ (posedge CLK_20MHZ) begin

numRow2 <= numRow;

case(adc_to_bridge)

0: datacount[7:0] <= ADC_E[7:0];

1: datacount[15:8] <= ADC_E[7:0];

2: datacount[23:16] <= ADC_E[7:0];

3: datacount[31:24] <= ADC_E[7:0];

4: datacount[39:32] <= ADC_E[7:0];

5: datacount[47:40] <= ADC_E[7:0];

6: datacount[55:48] <= ADC_E[7:0];

7: datacount[63:56] <= ADC_E[7:0];

endcase

if (numRow2 == 0 )

adc_to_bridge <= 0;

else

adc_to_bridge <= adc_to_bridge + 1;

end

always @ (negedge CLK_20MHZ) begin

if ( adc_to_bridge == 0)

datacount2 <= datacount;

end

always @ (negedge CLK_20MHZ)

if (numRow == 1 )

ADC_E <= { 6'b000000, numCol[11:10]};

else

if (numRow == 2 )

ADC_E <= numCol[9:2];

else

if (numRow == 316 )

ADC_E <= 255;

else

if (ADC == 255)

ADC_E <= 254;

else

case (number_ADC)

0:ADC_E <= ADC[7:0];

1:ADC_E <= ADC_A[7:0];

2:ADC_E <= ADC_A[8:1];

3:ADC_E <= ADC_A[9:2];

4:ADC_E <= ADC_B[7:0];

5:ADC_E <= ADC_B[8:1];

6:ADC_E <= ADC_B[9:2];

endcase

pll_0002 pll_inst (

.refclk (FPGA_CLK3_50), // refclk.clk

.rst (0), // reset.reset

.outclk_0 (CLK_20MHZpll), // outclk0.clk

.locked () // (terminated)S

);

command(

.clk9600(clk1Mhz),

.adress_from_UART(LED_from_hps[23:16]),

.UART_to_SPI(LED_from_hps[15:0]),

.adress(adress),

.adress2(adress2),

.adressN(adressN),

.D4_start (D4_start ),

.D4_stop (D4_stop ),

.D7_start (D7_start ),

.D7_stop (D7_stop ),

.D10_start(D10_start),

.D10_stop (D10_stop ),

.UART_to_SPI_Update(UART_to_SPI_Update),

.reverse(reverse),

.number_ADC(number_ADC)

);

generete_row_and_col_for_cheap (

.CLK_50MHZ(FPGA_CLK3_50),

.CLK_20MHZ(CLK_20MHZ),

.adress_from_UART(LED_from_hps[23:16]),

.UART_to_SPI(LED_from_hps[15:0]),

.D1(D1),

.D2(D2), //resV

.D3(D3),

.D4(D4),

.D5(D5), //clkV

.D6(D6), //rstH

.D7(D7),

.D8(D8), //ClkH

.D9(D9),

.D10(D10),

.numRow(numRow),

.numCol(numCol),

.D4_start(D4_start),

.D4_stop(D4_stop),

.countRow (D7_start ),

.countCol (D7_stop ),

.COM_TX_ON(0),

.clk960(clk960),

.D10_start(D10_start),

);

SPI (

.data(LED_from_hps[15:0]),

.adress(adress),

.adress2(adress2[1:0]),

.adressN(adressN),

.data_ready(UART_to_SPI_Update),

.clk(clk1Mhz),

.SPI_clk(SPIclk),

.SPI_data(SPIdata),

.SPI_en(SPIen)

);

endmodule

Ссылка на проект Quartus c этим кодом.

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